Floating gate memory devices which are programmed using hot electron injection and erased using Fowler-Nordheim tunneling are well-known and described in detail in U.S. Pat. Nos. 5,029,130 and 5,289,411. FIG. 1 shows an exemplary prior art floating gate memory array device 10 as disclosed in U.S. Pat. No. 5,289,411. The device 10 includes an array 40 of floating gate memory cells 42. The device 10 also includes an input buffer 12 which receives input data to be stored in the memory cells 42, a sense amplifier 16 which amplifies data signals read from the array 40, and an output buffer 14 which receives the read-out data signals from the amplifier 16. A column address decoder 18 receives a column address and generates an address signal on column address lines 26. A row address decoder 20 receives a row address and generates an address signal on row address lines 24. Each row address line 24 is connected to a row decoding circuit 50 which also receives row select lines 30 from a row select decoder 19. The output of the row decoding circuit 50 is a plurality of row lines 36. A pair of floating gate cells 42 are located at each intersection of the row lines 36 and a column address line 26. The device 10 further includes a high voltage (HV) source 22 which provides a high voltage potential for use in program and erase operations. The high voltage is supplied to a plurality of HV decoders 60 which each receive three HV select signals on lines 34 from an HV row select decoder 21. The HV decoders 60 are also connected to the row lines 36 from the corresponding row decoder 50.
The operation of the floating gate memory array device 40 is as follows. To program data in a given row of the floating gate memory cells 42, the selected row address line 24 is brought to Vcc potential. A threshold voltage Vt is supplied via the row decoder 50 to the first row line 36-1 in the given row and thereby to the gates of the memory cells 42 in that row. Source isolation transistors 44 are not turned on by the voltage Vt. A voltage of approximately +12 volts is supplied to the source of each of the cells 42 in that row via the second row line or N+ source line 36-2, the HV decoder 60 and the HV source 22. A given cell 42 in the activated row is programmed by bringing the corresponding column address line 26 and thereby the drain of the given cell 42 to either 0 volts or +5 volts depending on the logic value to be programmed. Hot electrons from the source of the given cell 42 can thereby be injected into and stored on the floating gate of the cell. The data stored in a given row of cells may be read back in a conventional manner. For example, the source of a given cell to be read can be brought to ground potential, the drain to a read voltage on the order of +2 volts and the gate to +5 volts. This will generate a signal indicative of the stored charge which is amplified by sense amplifier 16 and supplied to output buffer 14.
To erase data stored in the floating gate cells 42 of a given row of array 40, the row address line 24 for that row is activated. The row select decoder 19 supplies signals to row decoder 50 such that the first row line 36-1 connected to the gates of source isolation transistors 44 in the given row is held high while the second and third row lines 36-2 and 36-3 are held at ground potential. The source isolation transistors 44 are turned on to thereby connect a common ground line 32 to the second row line or N+ source line 36-2. The first row line 36-1 is then connected via HV decoder 60 to the high voltage from HV source 22. This supplies a potential of about +15 volts to the gate of each floating gate cell 42 in the given row. The column address lines 26 connected to the drains of each memory cell 42 in the given row are then brought to ground potential. The source of each of the memory cells 42 in the given row is also brought to ground potential via source isolation transistors 44 which connect the N+ source line 36-2 to the common ground line 32. The high voltage potential on the gate of the floating gate cells 42 causes the charge stored on the floating gate to be removed by the mechanism of Fowler-Nordheim tunneling.
The prior art floating gate memory array device 10 of FIG. 1 suffers from a number of problems. For example, the array 40 utilizes source isolation transistors 44 to isolate the high +12 volt source voltage used in programming a given cell 42 from other cells in the array. Although source isolation via transistor 44 can provide some reduction in program disturbance, the presence of the transistors 44 decreases the read current through a given cell and thereby degrades the read performance of the array device 10. Also, the programming current from HV decoder 60 runs through the entire length of an N+ source line 36-2 which is typically formed from high resistance N+ diffusion material. The programming current will thus result in a significant voltage drop across the source line 36-2 which can degrade programming efficiency and performance. Furthermore, the source isolation transistors 44 require chip space and thus result in an undesirable increase in the chip size for the memory array device 10. Another problem with the prior art memory array device 10 is that during a read operation, the signal Vcc-Vt is applied directly to the gates of a given row of memory cells 42 via the row lines 36-1 and/or 36-3. All of the cells 42 in the given row will therefore be stressed by the high Vcc voltage. Also, an increase or other disturbance in the supply voltage during a read operation can result in charges previously stored in the cells 42 being pulled away from the floating gates thereof via Fowler-Nordheim tunneling.
As is apparent from the above, there is a need for an improved floating gate memory array which exhibits improved read and program performance and eliminates the source isolation transistor requirement and other problems of the prior art.